Graph Neural Network-Based Power, Performance, and Area Prediction for Large-Scale Integrated Circuit Design Using GPU-Accelerated Learning
Keywords:
graph neural networks; integrated circuit design; power performance and area; GPU acceleration; electronic design automation; heterogeneous graphs; socio-technical infrastructure; design governanceAbstract
The increasing scale and heterogeneity of modern integrated circuits have made early prediction of power, performance, and area a central challenge in electronic design automation. Conventional analytical and simulation-based methods often struggle to balance accuracy, runtime, and scalability when applied to billion-transistor systems, especially during early architectural exploration and physical design. This paper examines graph neural network-based prediction of power, performance, and area for large-scale integrated circuit design using GPU-accelerated learning. It argues that circuit graphs provide a natural abstraction for capturing structural dependencies among cells, nets, macros, timing paths, and physical regions, while GPU acceleration enables the training and inference of large heterogeneous graph models at practical speed. The discussion focuses on system-level architecture, deployment trade-offs, data governance, robustness, fairness, and sustainability. It considers how heterogeneous graph learning can integrate logical, physical, and electrical features without reducing design intent to isolated local metrics. The paper further analyzes infrastructure requirements for distributed training, memory hierarchy constraints, graph partitioning, and workload scheduling. It also discusses the socio-technical implications of relying on learned predictors for critical design decisions, including explainability, accountability, reproducibility, and access equity across design teams and regions. Through cross-domain comparisons with molecular graph learning, combinatorial optimization, and large-scale language model training, the paper identifies structural lessons for scalable circuit intelligence. It concludes that graph neural networks with GPU-accelerated learning can become a foundational layer for predictive integrated circuit design, but only if technical performance is matched by governance mechanisms, robust validation, and sustainable compute practices.
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